1. Field
An embodiment of the present invention relates to the field of integrated circuit design, and more particularly, to design of a differential bus.
2. Discussion of Related Art
In microprocessors, for example, including large, high-speed on-chip cache memories has been shown to be a cost-effective way to improve microprocessor performance. Large on-chip cache memories provide for more data to be stored on-chip such that more time consuming off-chip memory accesses are reduced.
To take advantage of improved data locality provided by a large on-chip cache memory, it is desirable to have a high performance bus that can transfer data read from the cache memory to other parts of the microprocessor. It is also desirable for such a bus to be power and area efficient.
Designing such a bus can present many challenges. A full signal swing bus (i.e. signals communicated over the bus can transition rail-to-rail from a ground voltage to a power supply voltage) may consume an unacceptable amount of power and take up excessive space on the integrated circuit die.
A low voltage swing bus may consume less power and take up less space on the die, but there may be other disadvantages. For a typical low voltage swing bus, two bus lines are provided for each bit of information to be communicated and data is provided in the form of a differential signal. A sense amplifier enable (SAE) signal is used to sense data communicated over the bus. For one low voltage swing bus, the SAE signal is provided by a self-timed circuit wherein the data to be communicated is provided during one phase of a bus clock and the SAE signal is generated in a following phase. This approach can be slow and thus, not provide a high enough performance level for some applications. Further, the self-timed SAE signal may be difficult to control. Various factors such as non-uniformity in circuits across the processor or other integrated circuit device over which the bus traverses can lead to clock jitter, clock skew, noise, etc. that may each cause variations in the SAE signal. Looser bus timings may then be used to compensate for such variations.
For another low voltage swing bus, such as the bus 100 in FIG. 1, a self-timed SAE signal 105 provided by a SAE signal generator circuit 110 may be tunable to adjust the placement of the SAE signal rising edge. While a tunable self-timed SAE signal may provide for some additional control over the SAE signal 105 placement, for a high frequency microprocessor, for example, the tunable range may be limited. Further, providing a tunable SAE signal may be risky for such a high frequency device because, if the edge of the SAE signal is adjusted too far, the tuned SAE signal may cause erroneous data to be latched.
While a bus coupled to an on-chip cache memory is described above, it will be appreciated that other high performance integrated circuits that use an on-chip bus may present similar issues.
A method and apparatus to control a signal development rate for a differential bus are described. In accordance with one embodiment, an apparatus includes a differential bus and a differential signal development rate control circuit to control the development rate of a differential signal on the differential bus.
Other features and advantages of the present invention will be appreciated from the accompanying drawings and from the detailed description that follows below.